1. Field of the Invention
The present invention relates to a method for layout design and timing adjustment of a logically designed integrated circuit, particularly an ASIC (Application-Specific Integrated Circuit) using a gate array, that can be automatically laid out with a computer.
2. Description of the Related Art
With development to a higher degree of integration and function in semiconductor integrated circuit, a circuit scale thereof has increased, leading to a tremendous number of test patterns for failure detection. In order to attain a higher failure detection rate with a smaller number of test patterns, a scan pass method has been adopted for a semiconductor integrated circuit.
According to this method, in a case where an integrated circuit 10 as shown in FIG. 3 is logically designed, flip-flops 12 to 15 connected to a combinational circuit 11 are, as shown in FIG. 5, replaced with scan flip-flops (scan flip-flop) 12A to 15A having a normal operation mode and a scan mode, and the scan flip-flops 12A to 15A are cascaded to form a scan circuit. Each of the scan flip-flops 12A to 15A is of the same configuration and configured as shown in FIG. 6 for example. Although in FIG. 5, a circuit configuration is illustrated in a simplified form, the scan flip-flops actually lie scattered in the integrated circuit 10A. For this reason, in a case where the scan circuit is in the scan mode where the circuit works as a shift register, timing error tends to occur.
In a static timing analysis, the integrated circuit 10A is layout-designed, capacitance and resistance of wiring are calculated, thereby signal propagation delay times between cells are obtained, and thereafter whether or not timing error occurs is determined by calculation. In a case where it is determined that timing error occurs at an scan flip-flop, an scan flip-flop at the preceding stage is replaced by a cell of an scan flip-flop with a LUL (lock-up latch) 13B as shown in FIG. 7, for example, in order to cancel the error.
However, since the integrated circuit 10A is designed with a best fit layout and the scan flip-flop with a LUL is larger than an ordinary scan flip-flop in cell area, overlapping with an adjacent cell by cell replacement tends to occur. For this reason, rearrangement of cells and relayout of wiring become required, thereby leading to a possibility of causing a new timing error. If timing error occurs, requirement arises for redesigning and each time of layout design, timing verification and timing adjustment are to be followed, causing increase in development time.
This problem can be solved by constructing the scan circuit employing only scan flip-flops with LUL from the beginning.
In this case, however, a new problem occurs since not only does a circuit area increase but power consumption is also enhanced.
Especially, since delivery with short lead times is requested in a case of ASIC, requirement arises for a shorter development time for an integrated circuit. Furthermore, an integrated circuit for use in portable electronic equipment is required to be of lower power consumption for the purpose of a longer lifetime of a battery.
Accordingly, it is an object of the present invention to provide a method for layout design and timing adjustment of a logically designed integrated circuit capable of achieving both of a shorter development time and lower power consumption in a trade-off relation to each other.
In one aspect of the present invention, there is provided a method for layout design and timing adjustment of a logically designed integrated circuit including a first logic circuit, the first logic circuit including a plurality of flip-flops, the method comprising the steps of: (a) preparing cell data of first and second scan flip-flops, the second scan flip-flop comprising the first scan flip-flop and a latch circuit added to at a scan-out section of the first scan flip-flop; (b) producing a second logic circuit from the first logic circuit by replacing the plurality of flip-flops with respective the second scan flip-flops, and by connecting the plurality of scan second flip-flops in cascade to each other to construct a first scan circuit; (c) designing a layout of the second logic circuit; (d) obtaining a third logic circuit from the second logic circuit by replacing the second scan flip-flops with respective the first scan flip-flops to form a second scan circuit; and (e) performing a static timing analysis on the third logic circuit to adjust timing.
According to this configuration, since the second scan flip-flop is larger than the first scan flip-flop in cell area, no necessity arises for rearrangement of cells or relayout of clock wiring due to timing adjustment, thereby enabling reduction in the number of repetitions of timing adjustment and relayout, and decreasing in development time for an integrated circuit.
Moreover, since the second scan flip-flop is employed in only a part necessary for timing adjustment, lower power consumption in an integration circuit can be realized.
Therefore, both of a shorter development time and lower power consumption, which were in a trade-off relation to each other in the prior art, can be achieved.
Other aspects, objects, and the advantages of the present invention will become apparent from the following detailed description taken in connection with the accompanying drawings.